Each succeeding generation of semiconductor integrated circuits increase in speed and their features proliferate. Two factors govern the speed of signal transmission in semiconductor circuits: 1) switching time in the transistor portion, and 2) the time that an electrical signal is propagated in a circuit (wiring delay component). The switching time component tends to decrease with the reduction of transistor size, while the wiring delay component tends to increase with the refinement, i.e., diminution, in size of wiring layers and the increasing complexity of wiring circuitry. Since wiring delay is determined by the product (C×R) of wiring capacity C and wiring resistance R, the use of Cu as a material for wiring has been enthusiastically studied as a means of restricting wiring delay since it has a lower resistance than Al which has traditionally been used.
Damascene refers to a process in which interconnect metal lines are delineated by isolating dielectrics. Damascening is not performed by lithography and etching, but by chemical-mechanical planarization (CMP). In damascening, an interconnect pattern is first lithographically defined in the layer of dielectric, then metal is deposited to fill in the resulting trenches. Then excess metal is removed by means of chemical-mechanical polishing (planarization).
Chemical-mechanical polishing (CMP), also called chemical-mechanical planarization, refers to a method of removing layers of solid by chemical-mechanical polishing carried out for the purpose of surface planarization and definition of the metal interconnect pattern.
Dual damascene is a modified version of the damascene process which is used to form metal interconnect geometry using a CMP process instead of metal etching. In dual damascene, two interlayer dielectric patterning steps and one CMP step create a pattern which would otherwise require two patterning steps and two metal CMP steps when using a conventional damascene process.
FIG. 1(a) through FIG. (d) are drawings explaining a conventional method of manufacturing a semiconductor device having dual damascene structure wiring.
In a first conventional method of manufacturing a semiconductor shown in FIG. 1(a), a first silicon nitride (Si3N4) film 3, a first silicon oxide film 4, a second silicon nitride (Si3N4) film 5 and a second silicon oxide film 6 are successively formed over a layer insulation film 2 in which a first wiring layer 1 is embedded. The first wiring layers are formed on a substrate, not depicted in the drawings for the sake of brevity.
Next, as is shown in FIG. 1(b), anisotropic dry etching to open via hole 8 is performed using a first photoresist 7 as a mask. This etching is performed until the first nitride film 3 is exposed in the interior of via hole 8. The via hole 8 is also referred to as a contact hole. The first nitride film 3 acts as a stopper film that stops the progress of etching in this etching process as shown in FIG. 1(b).
When the etching to open via hole 8 is finished, the first photoresist 7 is removed from above the second silicon oxide film 6. Optionally, a second photoresist 9 which has an open portion that corresponds to the wiring slot 10 is formed in its place, as shown in FIG. 1(c).
Next, anisotropic dry etching to open wiring slot 10 is performed using the second photoresist 9 as a mask. This etching is performed under the condition that a silicon oxide film can be removed with a significant selection ratio to the silicon nitride film. At this time, the first silicon nitride film 3 and the second nitride film 5 are both used as stopper films which stop the progress of etching. Next, etching for the purpose of removing the second silicon nitride film 5 exposed in the bottom of wiring slot 10 and the first silicon nitride film 3 exposed in the bottom of via hole 8 is performed. If this processing is done properly, via hole 8 which exposes the surface of first wiring layer 1 and wiring slot 10 which leads to via hole 8 are formed as shown in FIG. 1(d).
In the latest generation (sub 0.25 μm technology and finer) semiconductors, deep UV lithography techniques are used to pattern the fine structure of gates and via holes. An antireflective coating (ARC) is commonly applied between the poly-Si and the photoresist to reduce undesirable reflections.
In a conventional art process, a method of forming a via-hole resist pattern includes applying an organic or inorganic ARC film 11, as is shown in FIG. 2(a) and in FIG. 2(b). The ARC can be an organic polymer such as PMMA (polymethyl methacrylate) or polycarbonate. The ARC can also be an inorganic material such as SiON or Ta2O5. This simplifies the process, but the antireflective coating film adhering to the side walls of the via hole becomes a mask when etching the layer insulation film around the via hole, and a layer insulation film residue 12 which has a fence configuration around the via hole occurs. FIG. 3 shows the fence around the via hole. Such layer of film residues with a fence configuration cause variations in the resistance value of the wiring layer.
When using this previously noted process, it is difficult to control the depth of antireflective film 11 in the etching back process. When this etching back process is conducted in oxygen plasma, the etching speed becomes very fast due to the etching speed planar distribution being non-uniform. Further, when etching with oxygen plasma in this way, the material that adheres to the walls of the reaction chamber of the dry etching device peels off due to exposure to the oxygen plasma. This detritus becomes particles which adhere to the semiconductor or device substrate, thereby causing contamination problems such as the formation of defects. While problems like these may be at least partially avoided by performing the etch back process in a special dry etching device, the manufacturing process for semiconductors thereby becomes highly complex and thus increases manufacturing costs.
As has been shown, conventional semiconductor processing forms fence structures around the via hole, and disadvantageous resistance variations in the wiring layer results. Further, conventional semiconductor processing causes contamination problems and the associated proliferation of defects.